Progress in integrated circuit technology has fostered digital signal processing systems (DSP's) for performing functions which heretofore were performed in the analog signal domain. Examples of such DSP's are digital television receivers, compact disc players and digital video interactive (DVI) systems.
There are two basic types of DSP's which are parallel bit systems, and bit-serial systems. Typically, parallel-bit systems have been employed for all systems processing relatively wide bandwidth signals because system operating rates are lower. That is, for a given sample bit width N, the parallel-bit systems operate at 1/N.sup.th the rate of bit-serial systems. However, the parallel-bit systems require significantly more circuitry than the bit-serial systems. Because of the greater complexity and larger power dissipation of parallel-bit systems it is desirable to realize many of the wide band systems with bit-serial circuitry. Unfortunately, the processing rates of such bit-serial systems are near or exceed the limit of current technologies.
Consider a video signal processing system operating at sample rates of 14.32 MHz with samples having bit-widths of 8 bits. A bit-serial system for processing such a signal must operate at clock rates of at least 115 MHz. Desirably the system will be realized in metal-oxide-semiconductor (MOS) technology because of its higher circuit density and lower power requirements. However, signal processing rates of 115 MHz tend to be very near the limit of current MOS technology.
One of the limiting factors is manifested by timing errors, particularly between different functional elements of a particular system. These errors result from the relatively low drive capability of MOS transistors. Nominally all of the functions on an DSP integrated circuit (IC) are operated synchronously with common clock signals. Now if an interconnection between functional elements tends to be longer than typical interconnections within a functional element, it will exhibit a larger capacitance. This larger capacitance can load the output of a functional element causing timing errors between elements and thus limit the speed of the overall system. Even within a functional element, connections may exist which exhibit a capacitance of sufficient value to create timing errors.
The present invention advantageously circumvents the adverse consequences of large interelectrode capacitances in bit-serial systems, thereby increasing the overall processing rate of such systems.